Package jaga.pj.circuits.fpgaft

Interface Summary

FaultModel	Interface for defining models of fault sequences.
FaultyCircuit
SingleFaultModel	Interface to collate all Single Fault Model classes which we'll know will only return a Point object from their nextElement() method.

Class Summary

CircuitPainter	For now only works with LUT circuits with 2 LUTins
CircuitPainterApplet
CircuitPainterObject
CircuitSimulatorPainterObject
ConnectedElementsFaultModel
FaultyOptimizedMapping	This will remove elements from the element array that aren't connected to the outputs in order to optimize the circuit simulation by avoiding refreshing unused gates.
FPGALUTAbsoluteMapping	FPGA LUT Structure is composed of CLBs containing a LUT and an Edge Triggered D-Latch.
FPGALUTVariableSizedAbsoluteMapping	FPGA LUT Structure is composed of CLBs containing a LUT and an Edge Triggered D-Latch.
FTLib	Collection of constants and methods used by the fpgaft package.
LastAddedFaultModel	Could add a memory loss variable to wipe out history now and then so it doesn't get filled..
LUTAbsoluteMapping	Genotype -> Phenotype mapping is:
LUTAbsoluteMappingVariableSized	Genotype -> Phenotype mapping is:
SimulatorEdgeDLatch
SimulatorFaultyCircuit	A circuit to be simulated.
SimulatorFaultyCircuitAsynchronous	Elements are not refreshed synchronously.
SimulatorFaultyCircuitOpt	A circuit to be simulated.
SimulatorFaultyDelayLE	Extend this class to make Logic Elements with efficient fault modelling.
SimulatorLUT	Faulty Logic Element with delay implementing a Lookup-Table of configurable inputs.
SingleFullFaultModel	A fault model where a sequence of all elements within a range are failed in several ways.
SingleRandomFaultModel	A fault model where a single element will fail at any time, but this element will be chosen randomly from a range of values.
SingleStaticFaultModel	A fault model where a single fixed element can fail in various ways.
SingleUsedFaultModel	Fault Model which iterates over the units used by this circuit.
SisOutputReader	Constructed with the output from the logic optimizer Sis, it will build a genotype to be mapped with the LUTAbsoluteMapping into a circuit.