jaga.pj.circuits.fpgaft
Class FPGALUTVariableSizedAbsoluteMapping

java.lang.Object
  |
  +--jaga.pj.circuits.fpgaft.FPGALUTVariableSizedAbsoluteMapping

All Implemented Interfaces:

CircuitMapping, java.io.Serializable

public class FPGALUTVariableSizedAbsoluteMapping

extends java.lang.Object

implements CircuitMapping

FPGA LUT Structure is composed of CLBs containing a LUT and an Edge Triggered D-Latch. The Variable Sized mapping differs mainly from the fixed size in that inputs are defined as addresses 0,1...nrIns -1. Genotype structure: First nrOuts * ( bitsPerVar + 1 ) define where to get outputs from, ala VassilevMapping.

The rest is divided into genes composed of three sections:

First 2^LUTInputs bits for the Look-Up Table.

Next LUTInputs * ( bitsPerVar + 1 ) bits define where to get inputs of LUT from.

Next bitsPerVar+1 bits define the input of the Latch.

See Also:

Serialized Form

Fields inherited from interface jaga.pj.circuits.CircuitMapping

ELEMENTS, INPUTS, OUTPUTS

Constructor Summary

FPGALUTVariableSizedAbsoluteMapping(int ins, int outs, int bpv, int lutIns, ElementDelayModel delMod)
Creates a new instance of FPGALUTMapping

Method Summary

SimulatorLogicElement	getElementFromAddress(SimulatorLogicElement[][] inoutels, int address)
SimulatorLogicElement[][]	map(BitSet individual) Takes and individual and an array of arrays of logic elements where this individual must be instantiated.
void	resetDelays(java.lang.Object delayDef)
java.lang.String	toString()

Methods inherited from class java.lang.Object

equals, getClass, hashCode, notify, notifyAll, wait, wait, wait

Constructor Detail

FPGALUTVariableSizedAbsoluteMapping

public FPGALUTVariableSizedAbsoluteMapping(int ins,
                                           int outs,
                                           int bpv,
                                           int lutIns,
                                           ElementDelayModel delMod)

Creates a new instance of FPGALUTMapping

Parameters:

ins - Number of Inputs to Circuit NOT including the Clock for the Latches.

outs - Number of Outputs to Circuit.

lutIns - Number of Inputs to Look-Up Tables.

bpv - Bits Per Variable, defines how many addressable CLBs there will be = 2^bpv-nrIns.

delMod - The generator of delay values.

Method Detail

map

public SimulatorLogicElement[][] map(BitSet individual)

Takes and individual and an array of arrays of logic elements where this individual must be instantiated.

Specified by:

map in interface CircuitMapping

Parameters:

individual - The individual to be mapped into a circuit.

Returns:

Array consisting of three subarrays: The first will represent the inputs to the circuit and is where the inputs will be fed in. The second represents the elements that are the outputs of the circuit and is where they will be read out from. The last is an array with all the elements of the circuit.

resetDelays

public void resetDelays(java.lang.Object delayDef)

Specified by:

resetDelays in interface CircuitMapping

toString

public java.lang.String toString()

Overrides:

toString in class java.lang.Object

getElementFromAddress

public SimulatorLogicElement getElementFromAddress(SimulatorLogicElement[][] inoutels,
                                                   int address)

Specified by:

getElementFromAddress in interface CircuitMapping