|
|||||||||
PREV CLASS NEXT CLASS | FRAMES NO FRAMES | ||||||||
SUMMARY: INNER | FIELD | CONSTR | METHOD | DETAIL: FIELD | CONSTR | METHOD |
java.lang.Object | +--jaga.pj.circuits.fpgaft.SisOutputReader
Constructed with the output from the logic optimizer Sis, it will build a genotype to be mapped with the LUTAbsoluteMapping into a circuit. The circuit must be mapped using the xl_* commands from Sis which use LUT + Latch technology. Then it must be printed using the commands print_io, print, print_latch in that order. This must be put into a file which is given to this class.
Field Summary | |
static int |
DEF_DELAY
|
static boolean |
DEFAULT_FPGA_MAPPING
|
static int |
DEFAULT_LUT_SIZE
|
static int |
DEFAULT_RESERVED_OUTPUTS
|
static boolean |
DEFAULT_SPACE_FOR_VOTER
|
static java.lang.String |
ELEMENT_DEF_TOKEN
|
static java.lang.String |
INPUT_DEF_START_TOKEN
|
static java.lang.String |
LATCH_DEF_START_TOKEN
|
static java.lang.String |
LATCH_INPUT_DEF_TOKEN
|
static java.lang.String |
LATCH_OUTPUT_DEF_TOKEN
|
static int |
LUT2_LATCH_SIZE
|
static java.lang.String |
OUTPUT_DEF_START_TOKEN
|
static java.lang.String |
SIS_DELIMETERS
|
Constructor Summary | |
SisOutputReader(java.io.File sisOut)
Number of LUT input defaulted to DEFAULT_LUT_SIZE, mapping defaulted to LUTAbsoluteMapping |
|
SisOutputReader(java.io.File sisOut,
int resOuts,
int lutInputs,
boolean FPGALUT,
boolean space4Voter)
|
|
SisOutputReader(java.io.File sisOut,
int resOuts,
int lutInputs,
boolean FPGALUT,
boolean space4Voter,
int extraBitsPerVar,
boolean varSized)
|
|
SisOutputReader(java.lang.String sisOut)
Number of LUT input defaulted to DEFAULT_LUT_SIZE , mapping defaulted to LUTAbsoluteMapping |
Method Summary | |
int |
calcAddEls(boolean FPGALUT,
boolean voterSpace,
int q,
int rq,
int tI,
int l,
int e)
Calculates the number of Elements which will need to be addressed, which in turn will be used to calculate the minimum number of bits per variable to use. |
static int |
calcBitsPerVar(int size)
Given the size of a circuit, returns how many bits per variable are the minimum necesary. |
static boolean[] |
extractTable(java.lang.String line,
int lutInputs)
Extracts n-input LUT truth table for this line of sis output. |
static java.lang.String[] |
extractUnitInputNames(java.lang.String line,
int lutInputs)
Given a line representing a unit definition from the Sis output, having the format X = [formula of Y0, Y1, Y2..] will return a String array with all the Yn |
int |
getBitsPerVar()
|
java.lang.String |
getGenotype()
|
static SimulatorLogicElement[] |
getInputsFromNames(java.lang.String[] inputNames,
java.util.Vector els,
java.util.Hashtable codes)
Given a String array with input names, and a hashtable with the elements, returns an array of elements. |
int |
getTotalEls()
|
java.lang.String |
getVassilevGenotype()
|
static int |
indexOf(java.lang.String pin,
java.lang.String[] hay)
|
static java.util.Vector |
scan4ElementNames(java.lang.String sisOut,
java.util.Vector outs)
Scans through the output from Sis in the format: print_io, print, print_latch and puts the names of the elements into a vector. |
static void |
scan4IOLNames(java.lang.String sisOut,
java.util.Vector inputNames,
java.util.Vector outputNames,
java.util.Vector latchNames,
java.util.Vector latchInputNames)
Scans through the output from Sis in the format: print_io, print, print_latch and puts the names of the inputs, outputs, latches and latch inputs into vectors. |
int |
sizeWithVoterBIST(int size,
int outs)
Returns the size of a voter with two copies of the circuit with a given size and number of outputs |
static java.lang.String |
vector2FPGAGene(java.util.Vector added,
SimulatorLogicElement[] globIns,
int bitsPerVar,
int lutInputs,
int nrOuts,
boolean varSized,
int reservedOutputs,
int nrLUTs)
|
static java.lang.String |
vector2Gene(java.util.Vector added,
SimulatorLogicElement[] globIns,
int bitsPerVar,
int lutInputs,
boolean varSized)
|
Methods inherited from class java.lang.Object |
equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait |
Field Detail |
public static final int DEF_DELAY
public static final int LUT2_LATCH_SIZE
public static final int DEFAULT_LUT_SIZE
public static final int DEFAULT_RESERVED_OUTPUTS
public static final boolean DEFAULT_FPGA_MAPPING
public static final boolean DEFAULT_SPACE_FOR_VOTER
public static final java.lang.String SIS_DELIMETERS
public static final java.lang.String LATCH_DEF_START_TOKEN
public static final java.lang.String LATCH_INPUT_DEF_TOKEN
public static final java.lang.String LATCH_OUTPUT_DEF_TOKEN
public static final java.lang.String INPUT_DEF_START_TOKEN
public static final java.lang.String OUTPUT_DEF_START_TOKEN
public static final java.lang.String ELEMENT_DEF_TOKEN
Constructor Detail |
public SisOutputReader(java.lang.String sisOut) throws java.io.IOException
public SisOutputReader(java.io.File sisOut) throws java.io.IOException
public SisOutputReader(java.io.File sisOut, int resOuts, int lutInputs, boolean FPGALUT, boolean space4Voter, int extraBitsPerVar, boolean varSized) throws java.io.IOException
public SisOutputReader(java.io.File sisOut, int resOuts, int lutInputs, boolean FPGALUT, boolean space4Voter) throws java.io.IOException
sisOut
- File containing output from sis from the commands print and print_latches one after the other.reservedOutputs
- Number of outputs to reserve, for eg. for evolving a circuit with BIST.lutInputs
- Number of inputs to Look-up Table units.FPGALUT
- True if we want the genotype to be usable with the FPGALUTAbsoluteMapping, False to be usable with the LUTAbsoluteMappingspace4Voter
- True if we want to reserve enough space for two copies of this circuit by increasing the number of addressable units.Method Detail |
public int calcAddEls(boolean FPGALUT, boolean voterSpace, int q, int rq, int tI, int l, int e)
public int sizeWithVoterBIST(int size, int outs)
public static int calcBitsPerVar(int size)
public static void scan4IOLNames(java.lang.String sisOut, java.util.Vector inputNames, java.util.Vector outputNames, java.util.Vector latchNames, java.util.Vector latchInputNames) throws java.io.IOException
public static java.util.Vector scan4ElementNames(java.lang.String sisOut, java.util.Vector outs) throws java.io.IOException
public static java.lang.String[] extractUnitInputNames(java.lang.String line, int lutInputs)
public static SimulatorLogicElement[] getInputsFromNames(java.lang.String[] inputNames, java.util.Vector els, java.util.Hashtable codes)
public static boolean[] extractTable(java.lang.String line, int lutInputs)
public static int indexOf(java.lang.String pin, java.lang.String[] hay)
pin
- What String we are looking for.hay
- Where to look for it.public static java.lang.String vector2Gene(java.util.Vector added, SimulatorLogicElement[] globIns, int bitsPerVar, int lutInputs, boolean varSized)
public static java.lang.String vector2FPGAGene(java.util.Vector added, SimulatorLogicElement[] globIns, int bitsPerVar, int lutInputs, int nrOuts, boolean varSized, int reservedOutputs, int nrLUTs)
public java.lang.String getVassilevGenotype()
public java.lang.String getGenotype()
public int getBitsPerVar()
public int getTotalEls()
|
|||||||||
PREV CLASS NEXT CLASS | FRAMES NO FRAMES | ||||||||
SUMMARY: INNER | FIELD | CONSTR | METHOD | DETAIL: FIELD | CONSTR | METHOD |